Open Architecture, Closed Borders: Inside the RISC-V Exception to US-China Tech Decoupling

A Rare Island of Cooperation

At Opentechwire, we've tracked semiconductor export controls as they've tightened month by month since 2022. GPU thresholds drop, lithography tools disappear from shipping manifests, and design software licences vanish. Yet one corner of chip development remains conspicuously open: RISC-V, the instruction set architecture that defines how processors decode commands. MIPS, the intellectual property provider acquired by GlobalFoundries in 2025, is now collaborating with Chinese firms "very closely" on RISC-V standardisation, according to chief technology officer Yankin Tanurhan. The partnership underscores a paradox that few policymakers have resolved - how to contain advanced chip capabilities whilst an open-source blueprint for processor design flows freely across borders.

RISC-V is not a physical chip. It is a specification, a shared language that tells silicon how to execute instructions. Because the architecture is open-source and maintained by a Switzerland-based non-profit, it sits outside the jurisdiction of the Bureau of Industry and Security. No export licence governs a text file. That legal vacuum has turned RISC-V into both a technical commons and a geopolitical anomaly.

Why an American IP House Is Betting on Shenzhen

MIPS built its reputation licensing MIPS-architecture cores, a proprietary instruction set that once powered Sony PlayStation consoles and Cisco routers. After GlobalFoundries acquired the firm, the strategy pivoted. Rather than defend a walled garden, MIPS began contributing its decades of processor design expertise to RISC-V standardisation. Tanurhan's remarks signal that China represents not a peripheral market but a core partner in that effort.

The rationale is straightforward. China has adopted RISC-V faster than any other region. Alibaba's T-Head division ships RISC-V cores for edge AI and automotive applications. Shenzhen-based startups are taping out RISC-V microcontrollers for Internet of Things devices at volumes that dwarf early ARM Cortex-M deployments. If RISC-V is to become the instruction set for the next wave of heterogeneous compute, the ecosystem needs Chinese fabs, Chinese tool vendors, and Chinese hyperscalers buying in. MIPS, even under an American parent, cannot standardise in isolation.

Collaboration here does not mean technology transfer in the traditional sense. MIPS is not handing over register-transfer-level code for a high-performance core. Instead, the firms are aligning on specification details: cache-coherence protocols for multi-core clusters, vector-extension encodings for machine-learning inference, interrupt-handling conventions for real-time operating systems. These are the mundane, essential negotiations that prevent fragmentation. If Chinese implementers and American IP vendors diverge on how a RISC-V core manages atomics, software written for one will break on the other, and the architecture loses the interoperability that makes it attractive.

The Limits Built into the Blueprint

RISC-V's openness is both its strength and its ceiling. The specification defines the interface, not the implementation. A RISC-V core running at 5 GHz with out-of-order execution, speculative prefetch, and advanced branch prediction is an engineering feat that requires thousands of person-years and access to leading-edge process nodes. The instruction set itself is silent on those details. This distinction matters for export control. Washington can still restrict the sale of electronic design automation software, the lithography machines that print sub-3nm features, and the high-bandwidth memory that feeds AI accelerators. A Chinese firm can implement RISC-V on a 28nm node for industrial controllers without touching any controlled technology. Moving that same design to 5nm for a data-centre processor requires ASML's extreme ultraviolet scanners and Synopsys' place-and-route tools, both of which remain on the Entity List for dozens of Chinese chip houses.

At Opentechwire, we've followed RISC-V deployments from Bengaluru to Hsinchu. The pattern is consistent: RISC-V thrives in applications where power and cost matter more than raw performance. Sensor hubs, motor controllers, wireless basebands. The architecture has yet to challenge x86 or ARM in the segments that Washington cares most about - server CPUs that train frontier models, mobile application processors that run encrypted messaging at scale. That gap is not an accident. It reflects the difference between specification and silicon, between open architecture and closed fabrication.

Standardisation as Strategic Hedge

For Chinese chip designers, RISC-V offers insurance against architecture-level sanctions. ARM, the dominant provider of mobile and embedded cores, is a UK firm with substantial US operations. Its instruction set is proprietary, and its licensing agreements are subject to export restrictions. In 2019, ARM reportedly suspended business with Huawei following US Department of Commerce guidance. RISC-V, by contrast, has no single owner to comply with a subpoena. The specification is public, the trademark is held by a Swiss foundation, and implementation requires no licence. A Chinese startup can download the latest ratified extensions, synthesise a core, and tape out a chip without asking permission from Santa Clara or Cambridge.

This structural advantage explains why Beijing has endorsed RISC-V in its national semiconductor roadmaps. It also explains why American firms like MIPS are willing to collaborate. If the architecture becomes the de facto standard for edge and embedded compute, US IP houses that contributed early will hold influence over the specification's evolution. Better to shape the standard from within than to cede the entire ecosystem to competitors. The calculation is tactical, not ideological.

The Geopolitical Tightrope

Tanurhan's comments arrive at a moment when US technology policy is more restrictive than at any point since the Cold War. The October 2023 semiconductor rule imposed sweeping controls on AI chips, advanced lithography, and the design software that connects the two. The 2024 update extended those controls to legacy nodes used in military applications. RISC-V remains untouched, but that forbearance is not guaranteed. Members of the US House of Representatives introduced legislation in 2023 that would require Commerce Department review of RISC-V contributions by US persons. The bill stalled, but the intent was clear: open-source is not a permanent sanctuary.

Industry groups have pushed back. RISC-V International, the governing body, relocated from Delaware to Switzerland in 2019 explicitly to insulate the architecture from unilateral export restrictions. The move bought time, but it did not eliminate risk. If Washington decides that RISC-V collaboration undermines its chip strategy, it has tools - entity listings for specific firms, "foreign direct product" rules that reach extraterritorially, visa restrictions for engineers attending working-group meetings. None of those measures are technically difficult. The question is whether the political cost is worth the strategic gain.

What This Means for the Next Wave of Silicon

The MIPS-China partnership is a signal, not an outlier. Other US firms - SiFive, Andes Technology's American partners, even Qualcomm in limited contexts - are engaged in similar standardisation efforts. The collaboration persists because RISC-V's value proposition depends on critical mass. An instruction set with fragmented implementations is worse than useless; it splinters toolchains, breaks binary compatibility, and forces software developers to maintain parallel codebases. Keeping Chinese implementers inside the tent reduces that risk.

For policymakers, the trade-off is uncomfortable. Allowing collaboration on RISC-V accelerates China's ability to design competitive processors for mid-tier applications, eroding the leverage that comes from ARM and x86 licensing restrictions. Blocking collaboration risks driving Chinese firms toward proprietary extensions that fork the architecture, creating a parallel ecosystem that US firms cannot influence and US software cannot target. Neither outcome is clean.

At Opentechwire, we see this tension playing out in private conversations at industry conferences - engineers who want to share errata fixes sitting next to export-control lawyers who flag every commit. The result is a patchwork: technical cooperation on the specification layer, strict compartmentalisation on implementation details, and a shared awareness that the rules could shift with the next legislative session.

The RISC-V story is not about decoupling. It is about the limits of decoupling when the technology in question is text, not transistors. As long as the instruction set remains open and the standard-setting body remains offshore, American and Chinese engineers will keep meeting in working groups, aligning opcodes, and drafting extensions. Whether that cooperation survives the next wave of export controls is an open question. For now, it endures - not because of trust, but because fragmentation costs more than collaboration.