Huawei Pushes Its Own Optical Standard Against Silicon Valley Incumbents

A New Front in the Chip Wars

On 10 September, Huawei unveiled near-package optics (NPO), a technical standard for integrating optical communication engines with processors. The move places the Shenzhen-based company in direct competition with Nvidia and Broadcom, both of which have backed co-packaged optics (CPO) as the preferred architecture for next-generation AI accelerators. At Opentechwire, we've tracked the growing importance of interconnect bandwidth in AI training clusters; this announcement marks the first time a major Asian equipment vendor has staked out a rival position on packaging topology.

NPO and CPO address the same bottleneck: moving training data between chips fast enough to keep thousands of AI accelerators fed. Both approaches place optical transceivers closer to silicon, cutting electrical-path latency and power consumption. Where they differ is proximity. CPO mounts the optical engine inside the same package as the main processor. NPO keeps it adjacent but separate, relying on high-speed electrical links across a short bridge.

Why Huawei Believes Proximity Beats Integration

According to Huawei, NPO is more practical to manufacture because it does not require co-design of electronic and photonic dies in a single thermal envelope. Existing assembly lines can handle NPO modules with minimal retooling, the company said, whereas CPO demands new processes for managing heat, optical alignment, and yield across heterogeneous materials.

That argument matters in a supply chain still grappling with advanced-packaging constraints. Fabs capable of hybrid bonding and through-silicon vias already face queues; adding photonics co-packaging would strain capacity further. By proposing a looser coupling, Huawei aims to tap the installed base of substrate manufacturers and outsourced assembly and test houses across China, Taiwan, and South-East Asia.

The technical trade-off is reach and signal integrity. CPO's tighter integration promises lower insertion loss and smaller footprint per lane, which becomes critical when scaling to 1.6-terabit or 3.2-terabit Ethernet ports. NPO accepts marginally higher electrical loss in exchange for manufacturing flexibility and the ability to swap optical engines independently of the main chip.

The Standards Battle Underneath

Standards in interconnect technology are rarely neutral. Nvidia has championed CPO in part because tighter integration raises the bar for would-be competitors: designing a competitive AI accelerator becomes harder when the optical layer is baked into the package. Broadcom, which supplies much of the custom silicon for hyperscale networks, sees CPO as a path to locking in switch-ASIC customers through proprietary co-packaging partnerships.

Huawei's NPO proposal inverts that logic. By keeping optics modular, the standard lowers the entry cost for merchant-silicon vendors and contract manufacturers. If NPO gains traction in China's domestic data-centre market, it could fragment the global installed base and complicate interoperability between US-designed and Chinese-designed AI clusters.

No formal standards body has yet endorsed either approach. The Optical Internetworking Forum and IEEE 802.3 working groups are monitoring both, but neither has published a final specification. Huawei's announcement functions as a pre-emptive move to shape those discussions and signal to domestic cloud operators which architecture will enjoy ecosystem support in China.

Supply-Chain Realities and Export Controls

Huawei's emphasis on existing supply chains is not purely technical. US export controls have restricted the company's access to cutting-edge lithography and electronic design automation tools. Building an AI-chip roadmap around CPO would deepen dependence on advanced nodes and packaging capabilities concentrated in jurisdictions subject to US influence.

NPO, by contrast, can be implemented with older process nodes for the electrical bridge and commodity optical components already produced at scale for telecom applications. That aligns with China's broader semiconductor strategy: achieve performance through architecture and integration rather than relying solely on leading-edge transistors.

The approach also reflects lessons from Huawei's own networking portfolio. The company has decades of experience designing optical transport systems and already integrates silicon photonics into its data-centre switches. Extending that competence into AI-accelerator packaging is a logical step, and one that plays to in-house strengths Nvidia and Broadcom lack.

What This Means for AI Infrastructure

If NPO becomes the de facto standard inside China, the AI infrastructure stack will bifurcate. Hyperscalers operating across both regions will face a choice: design dual-architecture clusters or accept performance penalties from protocol translation at the network edge. Component vendors will need to support two packaging ecosystems, raising R&D and inventory costs.

For AI labs and model developers, the implications are subtler. Training runs that span tens of thousands of accelerators are already sensitive to tail latency and bisection bandwidth. A shift from electrical to optical interconnects, regardless of packaging topology, will raise the performance ceiling. But if CPO and NPO clusters cannot interoperate seamlessly, the global pool of compute capacity fragments, potentially slowing the pace of frontier model development.

Huawei has not disclosed which customers have committed to NPO, nor has it published a timeline for commercial deployment. The standard remains a declaration of intent rather than a shipping product. Yet the announcement itself carries weight: it signals that China's largest equipment vendor believes the interconnect layer is too strategic to cede to US incumbents, and that manufacturing pragmatism can be a wedge against Silicon Valley's architectural ambitions.