CXMT Advances Toward 4F Square Memory Cell Design as China Narrows DRAM Gap

A Density Race That Never Sleeps

ChangXin Memory Technologies, the Hefei-based DRAM manufacturer better known as CXMT, announced over the weekend that it has reached what president Cao Kanyu described as "key progress" on a memory cell structure that has long defined the frontier of DRAM scaling. Speaking at an industry forum in Shanghai, Cao outlined plans to ship a server memory product built on the architecture before 2027 arrives - a timeline that, if met, would place CXMT within striking distance of the two South Korean giants that have dominated high-density DRAM for more than a decade.

At the heart of the announcement sits the 4F square design, a cell layout in which each memory capacitor occupies an area equal to four times the minimum feature size squared. The geometry matters because DRAM density - and ultimately cost per bit - hinges on how tightly you can pack capacitors and access transistors onto silicon. For years, the industry standard has been the 6F square cell; moving to 4F square represents a roughly 33 per cent reduction in cell area, all else being equal. Samsung and SK Hynix have both invested heavily in the transition, though neither has yet announced volume production of 4F square DRAM for the server market.

CXMT's disclosure is significant not for any single technical leap - 4F square cells have been discussed in research circles since the early 2010s - but for the signal it sends about China's ability to close the process gap under export controls that have, since late 2022, restricted access to the most advanced lithography and deposition tools. The fact that a Chinese manufacturer is publicly targeting the same cell architecture as Samsung and SK Hynix, and doing so on a timeline measured in quarters rather than years, suggests that equipment restrictions have slowed but not halted progress at the leading edge of memory.

Why 4F Square Matters for Server Workloads

Server DRAM is where the economics of density play out most visibly. Hyperscale data centres and AI training clusters demand modules with higher capacity per stick to maximise bandwidth and minimise the physical footprint of memory arrays. A 4F square cell allows manufacturers to either shrink die size - lowering cost - or increase capacity within the same die area. For workloads that are memory-bound - transformer inference, large-scale recommendation engines, in-memory databases - that translates directly into performance per watt and performance per dollar.

CXMT's move into this segment is also a bid for margin. Commodity DDR4 for consumer PCs, where the company has concentrated much of its volume to date, operates on thinner margins and faces intense competition from overstock and grey-market channels. Server DRAM, by contrast, commands higher prices and tends to be sold through longer-term contracts with OEMs and cloud providers. If CXMT can qualify a 4F square server product with even a handful of tier-one customers in China, it secures a revenue stream that is both more stable and more lucrative than the consumer market.

There is also a strategic dimension. China's government has for years identified memory as a chokepoint in the semiconductor supply chain, and CXMT - backed by the Hefei municipal government and a consortium of state-linked investors - has received sustained funding to develop domestic DRAM capacity. A 4F square rollout would mark the first time a Chinese DRAM maker has reached feature parity, at least in cell architecture, with the global leaders. That does not mean CXMT has caught up across the board - yield, reliability, and power efficiency are all separate battles - but it does mean the gap is no longer measured in generations.

The Lithography Question

Export controls imposed by the United States, the Netherlands, and Japan have restricted Chinese chipmakers' access to extreme ultraviolet lithography systems and certain high-end deep ultraviolet immersion tools. CXMT does not have EUV - neither does any Chinese fab - but 4F square DRAM can, in principle, be manufactured using multi-patterning techniques on older DUV steppers, albeit at higher cost and complexity.

What remains unclear is how CXMT has navigated the deposition and etch challenges that come with shrinking cell size. Capacitor height must increase to maintain charge storage as the footprint shrinks, and that requires high-aspect-ratio etching and atomic-layer deposition with tight process control. These are areas where US and European equipment makers - Applied Materials, Lam Research, ASML - have historically held commanding leads. CXMT has not disclosed its equipment lineup, but industry observers note that the company likely relies on a mix of pre-restriction tools, Chinese-made alternatives from suppliers such as AMEC and Naura, and process innovations that wring more performance out of older hardware.

The timeline Cao outlined - volume production by the end of 2026 - implies that pilot production is already underway and that yield is high enough to commit to a public schedule. That level of confidence suggests CXMT has either solved the equipment constraints or found workarounds that are good enough for initial qualification.

Samsung and SK Hynix Are Not Standing Still

Neither Samsung nor SK Hynix has been idle. Samsung's roadmap, disclosed in part at industry conferences over the past 18 months, includes a transition to 4F square cells as part of its fifth-generation 10-nanometre-class DRAM process, with volume production expected in the second half of 2026. SK Hynix has pursued a parallel path, emphasising not just cell scaling but also advances in through-silicon via stacking for high-bandwidth memory, which serves the AI accelerator market.

The difference is that the Korean manufacturers are targeting 4F square as one milestone in a continuous scaling roadmap that extends to sub-10-nanometre nodes and, eventually, to new memory architectures that may depart from the capacitor-based DRAM model altogether. CXMT, by contrast, is still catching up on current-generation density. Its most advanced product in volume production today is believed to be 17-nanometre-class DRAM - roughly two generations behind Samsung's leading edge.

What CXMT's 4F square announcement does, however, is compress the timeline. If the company can demonstrate reliable server DRAM at this cell size, it forces Samsung and SK Hynix to compete on price in segments where CXMT can underbid, particularly for customers inside China who face their own geopolitical pressures to diversify supply chains away from US-aligned vendors. That dynamic has already played out in NAND flash, where Yangtze Memory Technologies has captured share in the domestic market despite trailing in layer count.

A Server Product, Not a Research Milestone

It is worth underlining that Cao's statement referred to a product rollout, not a research demonstration. That distinction matters. Academic papers and conference presentations on 4F square cells have circulated for years; moving from a lab-scale proof of concept to a manufacturable product that passes qualification testing at server OEMs is a different order of difficulty. Yield must be high enough to be economically viable, defect density must meet customer specifications, and the product must survive thermal cycling, voltage stress, and long-term data retention tests.

CXMT's willingness to commit to a 2026 delivery date in a public forum suggests the company believes it can meet those requirements. Whether it can do so at a cost structure that competes with Samsung and SK Hynix - who benefit from decades of process learning and economies of scale - is a separate question. Early adopters in China may be willing to accept a price premium or slightly lower performance in exchange for supply security, but that calculus does not hold in export markets where CXMT faces both technical scrutiny and, in some jurisdictions, tariff and national-security barriers.

What This Means for the Memory Landscape

At Opentechwire, we have tracked the gradual maturation of China's memory sector since CXMT's first DDR4 shipments in 2019. The pace has been uneven - yield crises, equipment shortages, and management turnover have all slowed progress - but the trajectory has been consistently upward. The 4F square milestone, if delivered, would mark the point at which CXMT transitions from a follower executing on known processes to a competitor operating at the same architectural frontier as the incumbents.

That does not mean the gap has closed entirely. Process node nomenclature in DRAM is notoriously opaque, and a "4F square" cell at one manufacturer may not be directly comparable to another's due to differences in lithography, materials, and design rules. CXMT's 4F square product may still trail Samsung's in absolute density, power efficiency, or speed grades. But the gap is narrowing, and the fact that a Chinese DRAM maker is now publicly targeting the same cell architecture as the market leaders is a data point that memory buyers, equipment suppliers, and policymakers will all be parsing closely.

For the broader AI infrastructure market, the development introduces a new variable. If CXMT can supply cost-competitive server DRAM to Chinese hyperscalers and AI labs, it reduces their dependence on imports and potentially frees up Samsung and SK Hynix capacity to serve customers outside China. That could ease some of the supply tightness that has characterised the high-bandwidth and server DRAM markets over the past two years. It could also accelerate commoditisation in segments where CXMT competes, pushing the Korean manufacturers to invest even more heavily in next-generation architectures - HBM4, GDDR7, and eventually post-DRAM technologies - where the technical moat remains wide.

The server memory market is large enough, and growing fast enough, to support multiple suppliers. The question is not whether CXMT can participate, but on what terms - and how long it takes the rest of the industry to adjust.